台积电2026北美技术研讨会全文

Dr. Kevin ZhangSenior Vice President and Deputy Co-COOTSMC Booming Semiconductor Market Growth Semiconductor $1T Milestone Accelerated 2o30 Semiconductor Market by Platform TsMC Advanced Technology Roadmap A13 Extends Technology Leadership 97% optical shrink pushes density scaling to new heightsContinuous DTcO further enhances performance and power efficiencyBackward-compatible design rules with A14 ensure smooth IP migrationProduction is planned for 2029, one year after A14 6%Area Saving N2U Maximizes Technology Platform Values N2U further enhances PPA through DTCO to maximize technology valuesBackward-compatible DRM/SPICE ensure N2P IP reuse for best ROlWell suited for Al/HPC and Mobile applications for superior power efficiencyand process maturityProduction is planned for 2o28 CoWos? Enables Al Compute Scaling World's largest 5.5-reticle size CoWos in production with >98% yield in 2026Continue scaling with larger interposer size for growing Al compute demandwith 14-reticle (20xHBM) ready by 2028 and >14-reticle (24xHBM) by 2029 TsMC-SowTm Empowers System Integration System-on-Wafer (SoW) with wafer scale integration continuesinterposer size scaling to >40X reticle size (64xHBM) SoW-X offers a technology platform for logic + HBM integrationand will be in production in 2029 TsMC-Solc? Boosts Al Compute SolC with 3D interconnect offers 56X interconnect density and 5X power-efficiency over CoWoS with 2.5D interconnect 6μm pitch has entered volume production in 2025Continue scaling to A14-on-A14 with 4.5um pitch for production in 2029 System Integration Scales Al Compute Al compute scaling is driven by the combination of advanced logic, Solc 3Dstacking, and CoWos technologies From 2024 to 2029, Al compute transistors in one CoWoS will increase by 48X System Integration Scales Al Memory BW Al memory bandwidth is scaled by the combination of HBM progression,advanced logic for HBM base die, and CoWoS From 2024 to 2029, HBM bandwidth in one CoWoS will increase by 34X CPO with COUPE Enhances System Power Efficiency Co-Packaged Optics (CPO) with COUPE on Substrate provides 4X powerefficiency and 1oX latency reduction vs. Cu Wire COUPE on Interposer further enhances performance to achieve 1oX powerefficiency and 2oX latency reduction Automotive Embracing Physical Al -2X Silicon Content Enrichment Future of Al Systems: Humanoid RobotsFusion of Agentic Al and Physical Al Brain Sensing Reasoning & Decision MakingAP (VLAmodels)Connectivity (Wi-FiEthernet, Bluetooth) Environmental Perception CISMEMS·RadarlLiDAR MovementJoints & Motion Control:MCU PowerSystem Operations & Battery· PMIC Thank You TSMC 2026TECHNOLOGYSYMPOSIUM