长线视角：摩尔定律之后的半导体——堆叠技术走向舞台中央

Long View: Semiconductors beyond Moore's Law — Stacking totake center stage Chip and wafer Stacking to improve performance post Moore’s Law. It is welldocumented that Moore’s Law — or at least the economic part of it — is broken from belowaround 10nm. The memory wall — slow interconnection speed between memory andprocessor, relative to fast processor speed — is another bottleneck for the performance ofsemiconductor systems to be broken. Fortunately, advanced packaging — and specifically,stacking — is coming to the rescue. David Dai, CFA+852 2918 5704david.dai@bernsteinsg.com Juho Hwang+852 2123 2632juho.hwang@bernsteinsg.com Stacking increases the interconnection speed and hence performance of chips andis rapidly adopted in AI/HPC chips.A high performance computing chip in the futuremay employ many stacking technologies: processors (CPU or GPU) are made with BSPDN,integrated with 3D IC; memory made using CBA (CMOS Bonded Array) stacking, andstacked again into HBM and HBF (high bandwidth flash); finally, the processors, HBMs andHBFs are all integrated using CoWoS (or future technologies such as panel level packaging).However, the use cases are not limited to AI. Most of the DRAM and NAND chips, and manyof the advanced logic chips, will be made using stacking by 2030, no matter what theapplication is. Carmine Milano+44 20 7762 1857carmine.milano@bernsteinsg.com Jack Lin+852 2123 2683jack.lin@bernsteinsg.com We forecast the volume of chip/wafer stacking to grow 7x in 5 years. In 2025, weestimate that only ~500k wpm employed one of the stacking technologies, equivalent to7.4% of total wafer consumption. By 2030, we forecast the # of wafers that employ somestacking technology to reach 3,500k wpm, penetrating 37% of total wafer shipment. Ofthem, the biggest contributors are HBM, NAND CBA (CMOS bonded array) hybrid bonding,and DRAM CBA, while logic stacking (CoWoS, 3D IC, WMCM, BSPDN) will be smaller involume but big in value. Backend equipment companies continue to benefit.While investors are aware of ourpositive stance on backend equipment, it’s worth highlighting that it’s a long term trend (till2030 and beyond) and the applications are beyond AI. We like DISCO (OP, grinder/dicerfor stacking), Besi (OP, leader in die-to-wafer hybrid bonding), Tokyo Electron (OP, leaderin wafer-to-wafer hybrid bonding). Sumco (MP) will also benefit from increased raw waferbenefiting with stacking, despite our concerns on China competition. BERNSTEIN TICKER TABLE INVESTMENT IMPLICATIONS We rate DISCO (TP=¥60,800), Tokyo Electron (TP=¥39,400) and Besi (TP=€169.00) Outperform, Sumco (TP=¥1,230.00)Market-Perform. DETAILS CHIP AND WAFER STACKING TO IMPROVE PERFORMANCE POST MOORE’S LAW It is well documented that Moore’s Law — or at least the economic part of it — is broken from around 10nm (Exhibit 3). Back inthe days, with every node migration, fabricating transistors used to be cheaper. They no longer are. As a result, companies areincentivized to find other ways to extend Moore’s Law and make transistors cheaper while improving performance. However,today’s demands from AI on higher performance computing is ever stronger. This poses a challenge to make faster chips —logic, DRAM, NAND — and break the limit of slowing Moore’s Law. The memory wall — slow interconnection speed betweenmemory and processor, relative to fast processor speed — is another bottleneck for the performance of semiconductor systemsto be broken. Fortunately, advanced packaging — and specifically, stacking — is coming to the rescue. Stacking (Exhibit 2) includes 2.5D(putting multiple dies on top of an interposer) or 3D (putting dies on top of each other). By stacking, multiple chips cancommunicate quickly among themselves, and function as if it’s a single chip. This is most prominent in AI GPU or ASIC chips, andNvidia is the best example: a Hopper chip includes 2 GPU dies and 48 HBM dies (6 stacks of 8-hi HBM3), and Blackwell Ultraincludes 2 GPU dies and 144 HBM dies (12 stacks of 12-hi HBM3E), and soon Rubin Ultra will have 4 GPU dies and 256 HBMdies (16 stacks of 16-hi HBM4E, Exhibit 4). Besides improving interconnection speed, stacking is also getting adopted in the front end production process. The wafer-to-wafer stacking separates what was made in one wafer to two or more wafers. This has been adopted in CMOS Image Sensor(CIS) for years, and is recently seeing increasing adoption in NAND. We expect more wafer-to-wafer bonding will take place inDRAM and NAND CBA, as well as logic in the form of backside power (BSPDN). Exhibit 1 shows what a high performance computing chip in the future may look like by employing various stackingtechnologies. The chip consists of processors (CPU or GPU) which are made using chiplets integrated with 3D IC / hybridbonding. Each of the logic chiplets is made with BSPDN, which achieves better performance and shrinking by growing thepower connections from the back. Included in the same chip are HBM and HBF (high band