长期展望：超越摩尔定律的半导体——堆叠技术成为核心

LongView:SemiconductorsbeyondMoore'sLaw-Stackingtotake center stage Chip and wafer Stacking to improve performance post Moore's Law. It is welldocurnented that Mopre's Law r at least the econamic part ofit is broken frorn belowarourd 10nm. The memory wall slow interconneclion speed belween menory andprocessor, relative to fast processor speed is snother bottleneck for the performance ofsemiconducter systems to be broken. Fortunstely, advanced ps.ckaging ancl specifically.stacking is coming to the rescue. Devid Dal, CFA+852 2918 5704daidlligbemsleisgam +852 2123 2632Juhc Hwangjuho/wangxbermstxinsgcum Stacking increases the Interconnection speed and hence performance of chips andstacked again into HBM and HBF (high bandwicth flash): finally, the processors, HBMs andHBFs are all integreted using CowoS (or future technologies such as panel level packagingl.However, the use cases are not limitecl to Al. Most of the DRAM snd NAND chips, and manyof the ecivanced logic chips, will be made using stacking by 2030, no matter what theapplication is. Carmine Milanocarmina.milkanoternstensg.con+44 20 7782 1857 JocxUin+852 2123 2685 estimate that only 5O0k wprm ernployed one of the stacking technclogies, equivalent to7.4% of total waler consurnption. By 2030, we forecast the a of walers that ernploy somestacking technology to reach 3,500k wpr, penetrating 37% of total water shipment. Ofand DRAM CBA, while logic stecking (CoWoS, 3D IC, wMCM, BSPDN) will be smaller involume but big in value. Backend equipment companies continue to benefit. While investors are aware of ourpositive stance on backend equipnent, it's worth highlighting that it's a long term trend [ill2030 and beyund) and the aplications are beyond AI. We like DISCO (OP, grinder/dicerfer stacking). Besi (OP, leader in die-to-wsfer hybrid bonding), Tokyo Electron (OP, leaderin water-towster hybrid bcndingo. Sumco (MP) will alsc benefit trom increased raw waterbenefiting with stacklng, despite our concerns on Chine competitlon. BERNSTEIN TICKER TABLE INVESTMENTIMPLICATIONS We rate DISCO (TP=*6O,80O), Takyo Electron (TP=*39,40O) and Besi (TP=1B9.00) Outperfarm, Sumco (TP=×1,230.00)Market-Periorm. DETAILS CHIPANDWAFERSTACKINGTOIMPROVEPERFORMANCEPOSTMOORE'SLAW It is wel documented that Moore's Law or at least the econormic parl of it is broken from around 1Orm (Exhibit 3), Back inincentivized to find otier ways to extend Moore's Law and make transistors cheaper while improving performe/nce. However,todey s demends from Al on higher performence computing is ever stronger, This poses e. challenge to make faster chios.Iogic, DRAM, NAND end break the limit of slowing Mcore's Lew, The memory wall slow interconnection speed betweenmemcry and processar, relative to fast pracessor sperd is another bottlereck for the perfprmance pf semiconductar systemsto be braken. Fcrtunately, advanced packaging and specifically, stacking is coming to the rescue. Stacking (Exhibilt 2) includes 2.5D(putting multiple dies on top of an interposer) or 3D (putting dies on top of esch otherj. By stacking, multiple chips cancommunicste quickly smong themselves, and function as if it's s single chip. This is most prcminent in AI GPU or ASIC chips, andNviclia is the best exB/mple: e Hcpper chip includes 2 GPU dies e:1d 48 HBM dies (6 stecks of 8-hi HBM3), and Blackwell UItraincludes 2 GPU dies and 144 HBM cies [12 stacks of 12-hi HBM3E], and soon Rubin UItra will heve 4 GPU dies and 256 HBMdics (16 stacks of 16-hi HBM4E, Exhibit 4) Eesides inprowing intercornnection speed, sta:king is also getting iadapted in the front end production process. The wafer-to-waler slacking separales wnat was rnade in one wafer to two or more wafers. This has been adopled in CMO5 Image Sensor(CI5) for years, and is recently seeing increasing adopton in NAND, We expes1 more wrater-to-wafer bonding wil take place inDRAM and NAND CBA, as well as logic in the form of backsicle power (BSPDN) Exhilbit 1 shows what s high performance computing chip in the future may look lke by employing vsrious stsckingtechnologies, The chip consists of processcrs (CPU or GPU) which ere made using chiplets integreted with 3D IC / hybricbonding. Each of the logic chiplets is mece with BSPDN, vhich achieves better performance eand shrinking by growing thepcwer connections fram the back, Included in the same chip are HEM and HBF (high bancwidth flash) chips, which are DRAMand NAND dies conrected with stacking. Each DRAM and NAND die are made using CBA wafer te wafer bonding. Finally, theprocessors, HBMs and HBFs are allintegraled using CoWoS (or future lechnologies such as panel level packagingl. However, the use cases are rot limited to Al. Most of the DRAM and NAND chips, and many of the advanced logic chips, vill bemade using stacking by 2030, no matter what the aopolicationis. EXHI 3/T 2: Breakdown of multiple advanced packaging/staclking technologies STACKING VOLUMETOGROW7X IN5YEARS In 2025, we estimste that only ~500kw