代理式人工智能芯片设计的下一个飞跃

A new level of autonomy insemiconductor chip design is here Executivesummary Semiconductor engineering is entering aninteresting phase of AI adoption: moving fromanswering questions to executing governedworkflows. Agentic AI can automate connectedfront‑end and back‑end tasks such asspecification decomposition, RTL design,testbench generation, regression triage, DFT,PnR, Sign-off and technical documentation. The winning pattern is a multi‑agent system:smaller models for routine parsing andtemplating, selective use of stronger reasoningmodels for reviews, and non-LLM tools(compilers, linters, simulators, formal engines) asthe final source of truth.. To scale responsibly, teams must implement IPprotection, project isolation, human oversight forhigh-impact decisions, and traceable audit logsaligned to a recognizedCode of Ethics for AI. Why chip designhas been ‘AI‑slow’ –and what changed Chip design was slow to adopt AI because reliabilitymust be provable, not assumed. Historically,foundation models lacked a robust understandingof HDL and verification semantics, as well as thecross‑artifact dependencies that encode truedesign intent–RTL, System Verilog assertions,constraints, development flows, and EDA toolreports must all remain consistent. In siliconprograms, release schedules are tightly coupled tofoundry and DFM closure, making any“AI-suggested” change without sign-off evidenceoperationally risky. The defect cost curve is steep:CDC, reset, power-intent issues, or faulty sign-offcan trigger re-spins, yield loss, or field failures.Moreover, micro-architecture decisions and PPAoptimizations are core intellectual property, sostrict confidentiality constraints limit what can beexposed to general-purpose models. This shift raises a critical nextstep – understanding howagentic systems work andwhere they deliver value acrossthe chip development flow. What has changed is the emergence of tool-verifiedagentic workflows. Here’s what that looks like:Agentic workflows are like an assembly line – end-to-end processes made up of agents. “Toolverified” means that every action they take isbacked by deterministic evidence – compiled,linted, verified, simulated, and formally checked.Multi-agent orchestration3, 4, 5allows tasks to berouted based on complexity and workflow stage:smaller models handle parsing and templating,while more powerful models focus on reasoningand cross-artifact analysis. EDA tools remain anessential part of flow. This combination enablesmeaningful automation without compromisingsign-off discipline or engineering accountability. Assistants vsagentic AI: Thetechnical distinction Early AI adoption in engineering largely focused onassistants – tools that search, summarize, or generatecode snippets. While useful for individual productivity,they operate as isolated point solutions and do notmanage end-to-end workflows. Execution agents perform scoped actions, or script-based automation while validator agents rundeterministic checks – simulations, regressions, coverageanalysis and produce too - backed reports and evidence. Agentic AI, in contrast, introduces orchestration. It canplan multi-step tasks, invoke tools, observe outcomes,and iterate within defined policies and guardrails.In practice, an agentic system for chip verificationbehaves like a workflow engine. A planner starts with agoal, such as improving coverage closure into concretetasks, and decomposes it: Where agenticworkflows deliver valueacross the lifecycle Front‑end is the strongest fit since artifacts are text‑heavy and verifiable.Use cases include: Specs —› requirements:Convert prose into structuredrequirements with IDs andverification mapping. Back-end benefits are bounded as sign-off istool-driven. Agents can draft constraints, suggestQoR experiments, summarize timing/DRC/IR, andpropose ECOs – but all changes require formalvalidation. While the value is clear, practical adoption requiresa disciplined approach across data, modelorchestration, governance, and sustainability withinthe chip development flow. Applicability in thechip development flow Applying agentic AI in semiconductor design requirescareful consideration of several factors. These includewhere in the design flow it is deployed and the degree ofdependence on EDA tool–generated databases, whichoften limits autonomy due to proprietary constraints. Guardrails and data isolation are essential to protectsensitive IP, while the availability of high quality trainingdata is critical to reducing hallucinations and responsedrift. Finally, environmental impact and sustainabilitymust be factored in as compute usage scales. Data strategy:Quality over quantity Semiconductor datasets are inherently scarce becausethey are proprietary. As a result, reliability depends lesson data volume and more on curation and grounding. Aneffective strategy combines curated internal standards,retrieval augmented generation over approved designartifacts, and synthetic data to increase covera