多层电子系统的时间缩放理论

Electronic Systems Tingbo He Huawei Abstract For six decades, Moore's geometric scaling drove progress in semiconductors. That industrycompact no longer holds: returns from pure dimensional shrinking have flattened, leading-edgedesign budgets exceed one billion dollars per chip, and cost-per-transistor at the most advancednodes is no longer falling. This perspective argues for a successor scaling principle —τscaling —that adopts time itself, rather than transistor area, as the primary metric of progress, applying asingle characteristic time constantτas the unifying optimization target across twelve orders ofmagnitude,from a switching transistor to a data-center workload.Two production-scaledemonstrations are presented. On a mobile SoC,LogicFolding— a methodology that partitionsdigital, analog, and memory circuits across vertically stacked active tiers — delivers a 55% step-wise increase in transistor density and a 41% power-efficiency gain at a fixed device node. On AIsystems, a co-designed stack comprising the memory-semantic Unified Bus fabric, near-packagedHi-ONE optical I/O, and edge-to-surface 3D Folding projects more than 100× growth in hardwareintegration by 2035.The deeper claim is methodological:τscaling is the first scaling principle sinceDennard to establish a shared optimization target across the entire computing stack.ChinaXiv:202605.00224v1 Lead Since the mid-1960s, the semiconductor industry has measured progress in nanometers. Everyeighteen months, transistors shrank, frequencies rose, and the cost per logic gate fell. Moore's Law functioned as both an empirical observation and helped establish an industry compact upon whichthe entire computing stack was built. That industry compact no longer holds. Beyond the 7 nm node,geometric scaling no longer delivers its historical dividends. Lithography tooling is approachingthe physical limits of patterning, EUV depreciation dominates wafer cost, and the per-transistorprice curve has flattened — and in some cases reversed. For organizations whose access to the mostadvanced lithography is constrained, the constraint became binding earlier and bears down moreseverely. The central question for the industry has therefore changed. It is no longer"how much further canthe transistor shrink?"It is"what should be scaled, and against what objective?" Over the past six years, the author's team at Huawei Semiconductor has investigated this questionin silicon across mobile SoCs, AI accelerators, system fabrics, and packaging. The conclusion isthat the answer lies not in another node, nor in another transistor architecture, but in a change ofthe primary optimization target itself. This perspective argues that the next decade of electronic-system evolution should be guided not by geometric scaling, but by time scaling — the systematicreduction of a single characteristic time constantτacross every layer of the stack, from a transistorswitching in a picosecond to a data-center workload responding in a second.The case forτscaling is developed below as both a scientific methodology and an industrialroadmap, drawing on lessons from 381 chips brought to volume production between May 2020 andMay 2026.ChinaXiv:202605.00224v1 1. The End of the Geometric Era For most of its history, the semiconductor industry has had one job: make the transistor smaller.Gordon Moore's 1965 observation — that transistor density doubles approximately every twoyears— was complemented a decade later by Robert Dennard's scaling theory, which establishedthat proportional shrinking of voltage and dimensions could maintain a constant electric field.Together,geometric scaling and Dennard scaling delivered exponential improvements in performance per watt and performance per dollar for nearly five decades. This arrangement unraveled in two stages. Around 2005, Dennard scaling broke first: voltageceased to scale proportionally with feature size, and the dark-silicon era began. Geometric scalingpersistedlonger,sustained by FinFET and subsequently gate-all-around(GAA)devicearchitectures. Beyond 7nm, however, returns from pure dimensional scaling have flattened. Thereasons are now well documented: velocity saturation reduces the dependence of intrinsic delay onchannellength from quadratic to linear;the parasitic resistance and capacitance of localinterconnects increasingly dominate the standard-cell delay budget; mask costs, EUV depreciation,and design-rule complexity have driven leading-edge chip design budgets past one billion dollarsper chip at the 2 nm node. The economic consequences are equally inescapable. Cost per transistor has flattened at advancednodes and, at the leading edge, is now rising. The industry compact that sustained the last fiftyyears —more transistors at lower cost every generation— no longer holds.For Huawei Semiconductor, this transition arrived with an additional constraint: restricted accessto the most advanced lithography tooling. Assuming that another node would