面向硬件设计的多模态与多AI智能体

➢LLM Agents for Hardware Design➢Conclusion & Future Work •Growing number of transistors and more complex designs lead to long TAT•... •Opportunity: Leverage intelligent AI Agent to improve productivity and shorten TAT•Timing analysis agent (~days/weeks to mins)•Design rule checking code generation (~days to mins)•Verilog coding and debugging NVIDIA CONFIDENTIAL. DO NOT DISTRIBUTE.Source: IMEC Future Summits, May, 2022Source: Nvidia How to acquire domain capability and improve deployment efficiency •Capability acquisition methodsHardware Design Problems & Challenges for Agent DeploymentLLM Skill & Capability for Solving Hardware Design •Low to medium intellectual effort, lots of tedious works•Increase productivity, make designer’s life easier•By prompt: prompt engineering•By tools: RAG/customized tools/APIs •By decomposition: task flow, multi-AIs conversation•By learning: trial-and-error, experience accumulation •Extensive domain capability required to build usefulagents for chip design •Many knowledge comes from the designer’s insights•Need a framework that is easy to develop bydesigner •Diverse design knowledge: Logic design, physical design,verification, analog design, etc.•Diverse set of tool commands and file format:PrimeTime, ICC2,Innovus, reports, LEF/DEF,etcexperts•Low-code development •Library of Agents and ToolsCould we leverage LLM-based Agent in the real-world design flow? 4 (a) Task Flow Level(b)SubTaskLevel: Multi-AI Config(c) Agent Skill/ Capability Config ➢LLM Agents for Hardware Design➢Conclusion & Future Work SPICE Verification AgentMore Agent forHardware Design Overview of Our Agent Research for Chip Design NVIDIA CONFIDENTIAL. DO NOT DISTRIBUTE. VerilogCoder:Autonomous Verilog Coding Agents with Graph-basedPlanning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool•VerilogEvalBenchmark 94.2%pass •Dynamic Task Graph Planning•Task-DrivenCircuit KnowledgeGraph(TCRG) Retrieval•Code Completion&Debugging•Task-FlowDrivenMulti-Agent •AST-guidedwaveformdebugging tool•VerilogCoder+ MCTS: 98.1%Agentic Agentic(VerilogCoder+ MCTS)Agentic(VerilogCoder)Non-agentic(VerilogCoder)Non-agenticLlama3GPT4-Turbo Token Count: Non-agentic vs AgenticApprox. 13X more token count on average Waveform Debugging Dynamic Task Graph Solving + Multi-AI Collaboration + Customized Tool 14 DRC-Coder: Automated Design Rule Checking Code Generation DRV image from commercial tool.•Output: DRC code that can detect the DRC error correctly. •Programmer: Base on the design rule condition to write code•DRC Code Evaluation Tool 19 PPA AND LAYOUT-AWARE DEVICE CLUSTRING •Narrow down searching space•Assist finding routable + optimal layouts faster•Challenging to select a good set of LVS/DRC clean layouts for training:Routability+ PPA •RoutabilityCell Area PPA/ Compact Cell LayoutRoutability DiffusionBreak/Sharing•Limited amount of LVS/DRC clean layouts available in the early development stage of new technology node. Expert Designer Agent for Standard Cell Layout Optimization •Output: Adjusted and fine-tuned device clusteringconstraints •Contributions:•First to explore LLM for EDA optimization on an industrial-levelbenchmark. •Holistic assessments and studies on the capabilities anddomain knowledge of existing LLM on transistor level designs.•Achieve up to19.4%smaller cell area/ generate23.5%moreLVS/DRC clean cell layouts than previous work. NVIDIA CONFIDENTIAL. DO NOT DISTRIBUTE. Expert Designer Agent: LLM for Standard Cell Design LayoutOptimization •Netlist Tools•cluster_evaluator: Evaluate the quality of the cluster usingsimple cluster score.𝑠𝑐𝑜𝑟𝑒=෍(σ𝑛∈𝑁𝑐𝑑𝑃𝑛2+𝑁𝑛2𝑇𝑐+σ𝑛∈𝑁𝑐𝑔min(𝑃𝑛,𝑁𝑛)𝑇𝑐) 𝑐∈𝐶•get_MOSFETs_from_net: Traverse the circuit netlist tosearch and explore potential good clusters.Potential DiffusionSharable Nets in LayoutPotential Common Gatein Layout •440k lines in a report, 8k timing paths with relations between timing paths Hierarchical Plan Solving + Multi-Agent Collaboration ➢LLM Agents for Hardware Design➢Conclusion & Future Work •Extensive domain capability required to build useful agents for chip design•Diverse design knowledge: Logic design, physical design, verification, analog design, etc.•Diverse set of tool commands and file format:PrimeTime, ICC2,Innovus, reports, LEF/DEF, etc.•Agent capability comes from the designer’s insights NVIDIA CONFIDENTIAL. DO NOT DISTRIBUTE. •Incorporating PPA metrics into the agentic design flow •Developing more efficient self-learning techniques and memory systems for LLM agents for solving more complexhardware tasks •RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models•/NVlabs/RTLFixerGitHub repo•VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based 34NVIDIA CONFIDENTIAL. DO NOT DISTRIBUTE.•Large Language Model (LLM) for Standard Cell Layout Design Optimization•NTECH, Santa Clara, 2024 (Agents in Production)•LLM for Standard C