内存狂潮：四十年一遇的短缺如何引发内存繁荣

内存狂潮：四⼗年⼀遇的短缺如何引发内存繁荣 Pricesaredoublingagain,Supercycleisbigger,andcouldlastlongerthanyouthink 价格再次翻倍，超级周期规模更⼤，持续时间可能超出你的想象 DYLAN PATEL,RAYWANG,MYRONXIE,AND2OTHERS DYLAN PATEL、RAYWANG、MYRONXIE及其他2⼈ FEB07,2026 2026年2⽉7⽇∙PAID∙付费 Prices of memory are going crazy. SemiAnalysis has been calling this out for over a year sincelate 2024. The scariest thing is that we aren't even close to the peak. We go throughfab by fabproductionandexpansionversusdetailed end market demandby memory type toforecastmemory revenue, pricing, and marginbetter than anyone else. This has all been detailed intheSemiAnalysis memory modelfor a while, but we will share it more publicly today. Firstsome background. 内存价格正在疯狂上涨。SemiAnalysis⾃2024 年末以来⼀直在指出这⼀点，⾄今已超过⼀年。最可怕的是，我们甚⾄还远未达到峰值。我们逐个晶圆⼚分析⽣产和扩张情况，并对⽐按内存类型划分的详细终端市场需求，以预测内存收⼊、价格和利润率，这⽅⾯我们做得⽐任何⼈都好。这些内容在 SemiAnalysis 内存模型中已详细阐述了⼀段时间，但今天我们将更公开地分享。⾸先介绍⼀些背景。 TheInevitabilityofMemoryCycles:AHistoryofBoomsandBusts微信公众号 404K微信公众号 404K微信公众号 404K微信公众号 404K 内存周期的必然性：繁荣与萧条的历史 Since its commercial introduction in the 1970s, DRAM has benefited from the two scalinglaws that defined the semiconductor industry: Moore’s Law and Dennard scaling. The 1T1CDRAM cell, with one access transistor and one storage capacitor, scaled for decades.Shrinking transistors reduced cost per bit, while clever capacitor engineering preservedsufficient charge to maintain signal integrity. 微信公众号 404K微信公众号 404K微信公众号 404K微信公众号 404K⾃20 世纪 70 年代商业化以来，DRAM 受益于定义半导体⾏业的两⼤缩放定律：摩尔定律和登纳德缩放定律。1T1C DRAM 单元（⼀个存取晶体管和⼀个存储电容器）实现了数⼗年的缩放。晶体管的缩⼩降低了每⽐特成本，⽽巧妙的电容器⼯程则保持了⾜够的电荷以维持信号完整性。 For much of the industry’s history, DRAM density scaled faster than logic, doubling roughlyevery 18 months instead of 24 months and driving dramatic cost reductions. As acommoditized product, manufacturers needed to sustain cost-per-bit declines to staycompetitive. Suppliers who couldn’t compete on cost fell into a downward spiral: low sales left them short on cash tofinance next-generation nodes, which in turn left them further behindon cost-per-bit. Many DRAM producers fell victim and went into bankruptcy, resulting inconsolidation to just a few major players today. 在该⾏业历史的⼤部分时期，DRAM 密度的缩放速度快于逻辑电路，⼤约每 18 个⽉翻⼀番⽽⾮24 个⽉，推动了成本的⼤幅降低。作为⼀种商品化产品，制造商需要持续降低每⽐特成本才能保持竞争⼒。⽆法在成本上竞争的供应商陷⼊恶性循环：销量低导致缺乏资⾦投资下⼀代节点，这反过来又使他们在每⽐特成本上进⼀步落后。许多DRAM⽣产商成为受害者并破产，最终导致整合为今天仅剩的⼏家主要⼚商。 %% For more details on the industry and DRAM basics, check out our technical deep dive: 微信公众号 404K微信公众号 404K微信公众号 404K微信公众号 404K有关⾏业和 DRAM 基础知识的更多详细信息，请查看我们的技术深度解析： Yet DRAM scaling has slowed significantly over the past few decades, and density gains overtime have shrunk. Over the past decade, DRAM density has increased by only ~2× in total,versus roughly ~100× per decade during the industry’s peak scaling era. Capacitors are nowextreme three-dimensional structures with aspect ratios approaching 100:1, storing just tens ofthousands of electrons. For comparison, a small static shock when you touch a metaldoorknob might involve the transfer of billions of electrons. The static charge on just a speckof dust might be 10,000x what is stored in a modern DRAM cell. 然⽽，DRAM 的缩放速度在过去⼏⼗年中已显著放缓，密度增益也随时间⽽缩⼩。在过去⼗年中，DRAM 密度总共仅增加了约 2 倍，⽽在该⾏业缩放的巅峰时期，每⼗年的密度增长约为 100 倍。电容器现在已成为极端的三维结构，纵横⽐接近 100:1，仅存储数万个电⼦。相⽐之下，当你触摸⾦属门把⼿时产⽣的⼩静电冲击可能涉及数⼗亿个电⼦的转移。即使是⼀粒灰尘上的静电荷也可能是现代 DRAM 单元存储量的 10,000倍。微信公众号 404K微信公众号 404K微信公众号 404K微信公众号 404K Bitlines and sense amplifiers, once secondary concerns, are now dominant constraints. Everyincremental shrink reduces signal margin, increases variability, and raises cost. 位线和灵敏放⼤器曾经是次要问题，现在已成为主要制约因素。每⼀次微⼩的缩减都会降低信号裕度，增加可变性，并提⾼成本。 An easy way to understand the technical challenge in DRAM scaling is to think of a DRAMcell as a tiny bucket that holds electricity instead of water. Each bucket stores a bit of data byholding a small electrical charge. Over the years, engineers made these buckets smaller tofitmore memory on a chip. Atfirst this worked well. But today, those buckets are not just tallthey are tall and narrow, each is like a tiny drinking straw standing upright. Because of thesize each bucket now holds very very few electrons. 理解 DRAM 缩放技术挑战的⼀个简单⽅法是将 DRAM 单元想象成⼀个盛放电能⽽⾮⽔的⼩桶。每个桶通过保持少量电荷来存储⼀个⽐特的数据。多年来，⼯程师将这些桶做得更⼩，以便在芯⽚上容纳更多内存。起初这很有效。但如今，这些桶不仅⾼，⽽且又⾼又窄，每个都像⼀根直⽴的细吸管。由于尺⼨的原因，每个桶现在只能容纳⾮常⾮常少的电⼦。微信公众号 404K微信公众号 404K微信公众号 404K微信公众号 404K This is a problem. When the system tries to read the data, it has to detect this very faintelectrical signal and distinguish it from noise. The wires that connect these cells (the “bitline”)and the tiny sensors that read them (called sense amplifiers) are now the main bottleneck. Thesignal is so weak that even small variations in manufacturing or temperature can causeerrors. 这是⼀个问题。当系统试图读取数据时，它必须检测这个⾮常微弱的电信号并将其与噪声区分开来。连接这些单元的导线（"位线"）和读取它们的微型传感器（称为灵敏放⼤器）现在成为主要瓶颈。信号⾮常微弱，以⾄于制造或温度的微⼩变化都可能导致错误。 Together, these constraints explain why DRAM density has stagnated and why DRAM scalinghas slowed down significantly over the years. The collapse of DRAM scaling has far-reachingconsequ