DRAM技术扩展以满足未来需求：挑战与机遇

ISCA ’25 Tutorial: Scaling DRAM Technology to Meet Future Demands – Challenges & OpportunitiesISCA ’25 Tutorial: Scaling DRAM Technology to Meet Future Demands – Challenges & OpportunitiesWendy Elsasser is a Technical Director of Research Science at Rambus. She works in the Rambus Labs R&Ddivision investigating future system architectures and developing innovative solutions to address the impact onthe memory sub-systems. She has over 25 years of experience in industry, starting with semi-custom micro-controller design, test, and implementation. Over the last 20 years, her focus has been on memory sub-systems,primarily external DRAM. Her experience includes DRAM controller architecture, design, and validation as well asactive contributions to consortiums and standards bodies. Specifically, she was a leader in the Gen-Z consortiumand JEDEC, helping to define future memory interfaces and DRAM standards. Her work has resulted in 15 patents.Today’s PresentersTaeksang Songis a Corporate Vice President at Samsung Electronics where he is leading a team dedicated topioneering cutting-edge technologies including CAMM, MRDIMM, CXL memory expanders, fabric attachedmemory solutions and processing near memory to meet the evolving demands of next-generation data-centric AIarchitectures. He has 20 years’ professional experience in memory and sub-system architecture, interconnectprotocols, system-on-chip design and collaborating with CSPs to enable heterogeneous computing infrastructure.Prior to joining Samsung Electronics, he worked at Rambus Inc., Micron Technology and SK hynix in lead architectroles for the emerging memory controllers and systems. Taeksang received his PhD from KAIST, South Korea, in2006. He has authored and co-authored over 20 technical papers and holds over 50 U.S. patents.Steven Woois a Fellow and Distinguished Inventor at Rambus Inc., where he leads research in Rambus Labs onadvanced memory systems for accelerators and computing infrastructure, and manages a team of seniorarchitects. Since joining Rambus, Steve has worked in various roles leading architecture, technology, andperformance analysis efforts, and in marketing and product planning roles leading strategy and customerprograms.He has more than 25 years of experience working on advanced memory systems and holds more than100 US and international patents. Steve received his PhD and MS degrees in Electrical Engineering from StanfordUniversity, and Master of Engineering and BS Engineering degrees from Harvey Mudd College. Introduction: Markets and History first described Charge on capacitor represents “0” or “1”Access transistor to read and write a bit cellDynamic: Bit cells are volatile (lose charge over The Fundamental DRAM Building Block: The 1T1C Bit Cell Host (CPU or GPU) Package InterfaceTimingCircuitsDRAM siliconSubstrate Interface: Circuits that interface to the hostCore: Bit cells and supporting logic •••DRAM Interface and Core Example Latency Under Load Curves Resilience to circuit/DRAM failures, disturb effects(e.g., RowHammer), Silent Data Corruption (SDC) =>increasingly important for future DRAMs and systemsCost/bit of DRAM, system cost (2.5D packaging, Cost/bit and system costinterposers, power components, buffer chips) ECC/Reliability Some Important DRAM and Memory System Characteristics ISCA ’25 Tutorial: Scaling DRAM Technology to Meet Future Demands – Challenges & OpportunitiesISCA ’25 Tutorial: Scaling DRAM Technology to Meet Future Demands – Challenges & OpportunitiesSeveral types of DRAMs, all use the 1T1C bit cell to store dataLow active and idle power withspecial low power modesFast wake up and power downsupports bursty system activity•Low profile supports stackingwith processor die Mobile •• DRAM interfaces and packaging differ based on how DRAMs are used in the system Different DRAMs for Different Markets•DRAMs packaged on modules(DIMMs, CAMMs)•Multiple DRAMs service oneRead and Write transaction•Can tolerate failure of 1 DRAM MDBs mux andde-mux two6.4GT/s DRAMhost interface RDIMM Low active and idle power with special low power modesSpecial low power modes support system sleep modesFast wake up/power down supports bursty memory systemactivity, fast transitions between active and sleep modesLow profile supports stacking with processor die PCB Graphics Memory: GDDRHighest data rates, challenging signal integrityNvidia RTX5090 Interposer AMD MI325X SoC PHYPower33.3%DRAM CorePower37.4% DRAMInterface +Channel IO Power29.3% HBM2 Memory System PowerPHY + DRAM Power at 2Gbps, Streaming ReadsSoCPHY1024 Memory is major portion of server costAt data center scale, underutilized resourceshave big TCO impact•Data center workloads becoming more diverseas new use cases evolve•Want to compose infrastructure as needed,adapt to workload needs•CPUs, memory, storage lifecycles different =>replace separately to improve TCO CXL, composability offer the potential to improve TCO Compute Node Component Costs Memor