Chinese Semiconductor: Tech Future: AI Data Center Networking Basics

Future of Tech: AI Datacenter Networking Primer As AI model sizes and computational requirements scale exponentially, single chips are nolonger sufficient. Modern AI workloads demand massive clusters of accelerators that mustoperate as a unified computing fabric, making AI datacenter (AIDC) networking a criticaldeterminant of system level efficiency. As a result, we see AIDC networking evolving into Stacy A. Rasgon, Ph.D.+1 213 559 5917stacy.rasgon@bernsteinsg.comFrancis Ma+852 2123 2626francis.ma@bernsteinsg.comZheng Cui Demand for AIDC networking chips is exploding due to the compound bandwidtheffect, with a TAM roughly estimated to reach USD ~100Bn in 2030 with ~30% CAGR. For multi-tier networking structures needed for large scale clusters, adding asingle accelerator increases not only point to point bandwidth, but also multiplies trafficacross higher tiers of the cluster and needs to add a lot more networking components.When the number of chips exceeds certain threshold, it is also required to add more layersof connections. This compounding behavior means that total network throughput rises +852 2123 2694zheng.cui@bernsteinsg.comArpad von Nemes+1 917 344 8461arpad.vonnemes@bernsteinsg.com AIDC networking can be categorized into three major connection types.DC-DCconnectionsfocus on wide area bandwidth and reliability across multiple DCs;CPU-centric connectionsmanage data flows between CPU and accelerators/NICs/SSDetc.; andxPU-to-xPU connections(GPU/TPU/NPU) deliver the high bandwidth and low Alrick Shaw+1 917 344 8454alrick.shaw@bernsteinsg.com latency pathways needed to form large AI compute clusters. Within xPU-to-xPU,scale-upnetworks connect multiple chips and share the computing power so they perform logicallylike one chip (or ‘node’), whilescale-outnetworks stitch thousands of ‘nodes’ across a Competition in the scale-up networking domain remains intense and far from settled.Nvidia’sNVLinkstill sets the performance benchmark with tight hardware-software integration and proven performance, but industry players are pushing alternativeapproaches as it’s a closed system.UALinkand Ethernet based SUEarchitectures aim tochallenge Nvidia by promoting open ecosystems, reduced vendor lock-in, and lower coststructures.PCIecontinues to gain traction with cloud service providers seeking mature,inexpensive solutions for certain workloads. Meanwhile, China may pursue a distinct path: For networking vendors, the sector offers strong industry beta and structurallyattractive margins.The technological and capital barriers in high-performanceinterconnects are immense, limiting new entrants and result in high margins.Nvidia/Huaweirepresent a closed ecosystem that benefits from a fully integrated end-to-endfabric across computing and networking.Broadcom/Marvellstands to gain share from INVESTMENT IMPLICATIONS We rate Hygon and Cambricon Outperform, with TP at CNY 280 and CNY 2,000, respectively. NVDA (Outperform, $300 PT):The datacenter opportunity is enormous, and still early, with material upside still possible. AVGO (OP, $525 PT):A strong 2025 AI trajectory seems set to accelerate into 2026 and beyond, bolstered by software, cashdeployment, and superb margins & FCF. Table Of Contents Networking becoming a key pillar in AI infrastructure............................................................................................................................................... 3Sizing the TAM for AIDC networking chips............................................................................................................................................................. 3The compound bandwidth effect................................................................................................................................................................................6Architecture of AIDC network..............................................................................................................................................................................................9Three connectivity layers in AIDC network..............................................................................................................................................................9Protocols applicable to each connectivity layer................................................................................................................................................. 11Silicon hardware enabling AIDC network..............................................................................................................................................................13 DETAILS NETWORKING BECOMING A KEY PILLAR IN AI INFRASTRUCTURE SIZING THE TAM FOR AIDC NETWORKING CHIPS In the Gen AI era, networking has transcended its legacy role as a peripheral utility to become one of the core bottlenecks in theAI infrastructure, on par with compute accelerators and memory. As LLMs scale toward trillions of