超越铜的互连技术、1000个CFET、SK海力士下一代NAND、二维材料等更多内容

超越铜的互连技术、1,000个CFET、SK海⼒⼠下⼀代NAND、⼆维材料等更多内容 IEDM2025Round-Up IEDM2025综述 GERALDWONG,JEFF KOCH,RANDY,AND2OTHERS 杰拉尔德·王、杰夫·科赫、兰迪及另外2⼈ JAN14,2026 2026年1⽉14⽇∙PAID∙付费 It’s an odd time in the chipmaking industry. On one hand, we are ramping into the biggestsupercycle ever seen. Advanced logic, DRAM, NAND, customers can’t get enough,chipmakers can’t build capacity fast enough, and we may soon be limited by fab equipmentsupply. On the other hand, the rapid technology improvement in scaling, power consumption,chip cost, etc. have slowed to a crawl. Massive research efforts yield small incremental gains.As costs increase but improvements asymptote and scaling runs out of room at the bottom, itsometimes feels like Moore’s Law has become Moore’s Wall. 这是芯⽚制造⾏业的⼀个奇特时期。⼀⽅⾯，我们正在迈⼊有史以来规模最⼤的超级周期。先进逻辑、DRAM、NAND——客户需求旺盛到供不应求，芯⽚制造商的产能建设速度远远跟不上，我们甚⾄可能很快会受到晶圆⼚设备供应的限制。另⼀⽅⾯，在制程缩放、功耗、芯⽚成本等⽅⾯，技术进步的速度却已放缓到⼏乎停滞。巨额的研发投⼊只能换来微⼩的渐进式提升。随着成本不断上升，⽽改进逐渐趋于饱和、缩放在物理极限处逐步失去空间，有时不禁让⼈感觉，摩尔定律已经变成了“摩尔之墙”。 The good news is the semiconductor industry has a long history of making naysayers lookstupid in the long run. There are plenty of innovations on the bench that are promising forthe next decade and beyond. In this report, as with2022,2023, and2024, we’ll cover highlightsfrom IEDM 2025 tofind out what the future of chipmaking might look like. 好消息是，半导体⾏业在长期内⼀直有让唱衰者看起来很愚蠢的历史。实验台上有⼤量前景可期的创新，有望⽀撑未来⼗年乃⾄更长时间的发展。在本报告中，如同 2022年、2023 年和 2024 年⼀样，我们将回顾 IEDM 2025 的重点内容，来⼀窥芯⽚制造的未来可能呈现的样貌。 With memory prices exploding, 3D NAND technology is suddenly relevant again. We’ll lookat the technology and competitiveness of SK Hynix’s latest V9 NAND, Samsung’s use of Moto improve its existing V9 products, and a big innovation that we may see in futureproduction from SK Hynix. For advanced logic, we’ll look at interconnect metals beyond Cu,the potential of 2D materials to replace Si in transistors, and the progress in CFET, the next big inflection after gate-all-around. 随着存储器价格飙升，3D NAND 技术突然再次变得重要起来。我们将探讨 SK 海⼒⼠最新的 V9 NAND 的技术与竞争⼒、三星利⽤Mo 改进其现有 V9 产品的做法，以及未来可能在 SK 海⼒⼠量产中看到的⼀项重⼤创新。在先进逻辑领域，我们将关注超越Cu 的互连⾦属、⽤2D 材料取代晶体管中 Si 的潜⼒，以及作为全环绕栅极（gate-all-around）之后下⼀个重⼤拐点的 CFET 的进展。 3D NAND NAND scaling is critically relevant right now, as demand is spiking but there is no cleanroomspace for building out capacity. Memory producers are limited to upgrading existing lines, sotheir supply is constrained by how dense their upgraded process is. For leading fabs, this is a3xx-layer 3D NAND process, which yields on the order of 20-30 Gb/mm2of memory. Thatpencils out to 30+ TB of memory on a single 12” wafer (note the difference between (b)its and(B)ytes in these abbreviations). 当前，NAND 缩放尤为关键，因为需求正在激增，但并没有额外的洁净室空间来扩建产能。存储器⼚商只能对现有产线进⾏升级，因此其供给能⼒受限于升级后⼯艺的存储密度。对于领先的晶圆⼚⽽⾔，这通常是 3xx 层的 3D NAND⼯艺，其存储密度约为 20–30 Gb/mm2。换算下来，单⽚12 英⼨晶圆可提供 30 TB 以上的存储容量（注意这些缩写中 (b)⽐特与 (B) 字节之间的差异）。 3D NAND:Hynix321Layer3D NAND：海⼒⼠321层 In the case of SK Hynix, the 321-layer process has 44% more memory per wafer than theprevious generation 238-layer technology. If you are constrained by cleanroom space and byextension the number of wafers you can produce, 44% more memory on each of those wafersmakes upgrades an obvious choice. 以 SK 海⼒⼠为例，其 321 层⼯艺相⽐上⼀代 238 层技术，每⽚晶圆的存储容量提升了44%。如果受限于洁净室空间，进⽽受限于可⽣产的晶圆数量，那么在每⽚晶圆上增加 44% 的存储容量，⽆疑使⼯艺升级成为显⽽易见的选择。 We’ve written in detail aboutNAND scaling methods, as a quick recap: 我们已经详细撰写过有关 NAND 缩放⽅法的内容，下⾯是⼀个简要回顾： There are 4 main avenues for scaling the storage capacity of NAND Flash per wafer. 按每⽚晶圆计算，扩展 NAND 闪存存储容量主要有四条途径。 1. Logical scaling – The number of bits stored per cell. This requires storing 2^n voltagelevels per cell. 1. 逻辑缩放——每个存储单元中存储的⽐特数量。这需要在每个单元中存储 2^n 个电压等级。 2. Vertical scaling – The number of NAND cells stacked vertically 2. 垂直缩放——垂直堆叠的 NAND 存储单元数量 3. Lateral scaling – The size/number of cells that can befit on the 2D vector 3. 横向缩放——在⼆维平⾯上可容纳的单元尺⼨/数量 4. Architecture scaling – Various techniques to increase density and reduce overhead fromcells/periphery. 4. 架构缩放——通过多种技术提⾼密度并降低单元/外围电路的开销。 Remember that NAND is just about cramming as many storage cells onto the wafer aspossible. This manifests in 3D NAND as vertical cylinders, channels, packed tightly togetherlike trees in a forest. Flat layers, alternating between conductive and insulating material,surround these channels. A memory cell is formed at each intersection of channel andconductive layer. 请记住，NAND 的核⼼⽬标就是在晶圆上尽可能多地塞⼊存储单元。在 3D NAND中，这体现在垂直的圆柱形通道上，这些通道像森林中的树⽊⼀样紧密排列。平坦的层状结构在这些通道周围交替分布，由导电材料和绝缘材料组成。在通道与导电层的每⼀个交点处，都会形成⼀个存储单元。 典型的 3D NAND 架构。垂直通道与交替排列的导电层和绝缘层相交。在每⼀个导电层的交点处形成⼀个存储单元。来源：Lam Research The memory cells are read and written based on charge held in a charge trap material, a layersurrounding each of the vertical channels. Charge stored there changes the threshold voltage(i.e. minimum voltage required to switch the transistor on) of the transistor. The cell can beread as 1 or 0 based on whether it switches at a given threshold voltage. 存储单元的读写基于存储在电荷陷阱材料中的电荷，该材料是⼀层包围每个垂直通道的结构。存储在其中的电荷会改